docs: document Phase 1 perfboard carrier state and Phase 2 English console BOM

README.md

@@ -5,74 +5,79 @@
 [![KiCad](https://img.shields.io/badge/EDA-KiCad%2010-314CB0?style=for-the-badge&logo=kicad&logoColor=white)](https://www.kicad.org/)
 [![Language](https://img.shields.io/badge/Firmware-C99%20%2F%20C%2B%2B-00599C?style=for-the-badge&logo=c)](https://en.wikipedia.org/wiki/C_(programming_language))
 [![RTOS](https://img.shields.io/badge/OS-FreeRTOS-008080?style=for-the-badge)](https://www.freertos.org/)
-[![Status](https://img.shields.io/badge/Status-Active%20Prototype-success?style=for-the-badge)](#roadmap--milestones)
+[![Status](https://img.shields.io/badge/Status-Phase%201%20Carrier%20Complete-success?style=for-the-badge)](#project-status--roadmap)
 
-A custom, high-performance handheld remote controller engineered from scratch for dual-role applications: **long-range, low-latency RC vehicle control** and **USB/Bluetooth HID gaming**.
+A custom, modular remote controller and telemetry station engineered from scratch for **long-range, low-latency 2.4 GHz RC control** and **USB/Bluetooth HID gaming**.
 
-Built around the **ESP32-S3-N16R8 (Xtensa® 32-bit LX7 dual-core @ 240 MHz)**, this project bridges hardware and software engineering—combining analog/Hall-effect sensing on `ADC1`, 2.4 GHz nRF24L01+ RF telemetry, hardware pulse-counted (`pulse_cnt`) rotary inputs, and a shared high-speed `SPI2_HOST` (FSPI) bus driving both the 1.3" SH1106 OLED display and radio transceiver without bus collisions.
+Built around the **ESP32-S3-N16R8 (Xtensa® 32-bit LX7 dual-core @ 240 MHz)**, this project is developed in structured hardware phases—starting from a hand-wired 6×9 cm perfboard carrier core and scaling into a full desktop/console transmitter housed in a **DT-100 (190 × 137 × 59 mm)** instrument enclosure.
 
 ---
 
-## Prototype Showcase
+## Phase 1: Core Carrier Board Showcase (Current Build)
+
+The current physical hardware implements the **Core MCU & RF Carrier Stage** on a 6×9 cm perfboard:
+- **ESP32-S3-N16R8 Microcontroller** (socketed on female headers)
+- **nRF24L01+ 2.4 GHz RF Transceiver Module** with external dipole SMA antenna
+- **100 µF Electrolytic Decoupling Capacitor** (`C1`) across the 3.3V/GND radio rails to suppress TX burst voltage droop
+- **Modular Male Pin Headers & Dedicated Power Rail Headers** for external display, encoder, and joystick breakout interfacing
 
 <p align="center">
   <img src="images/TOP_VIEW.png" alt="Multi-Functional Controller Top View" width="700">
   <br>
-  <em><b>Figure 1:</b> Top assembly layout — ESP32-S3-N16R8 module, analog joystick, quadrature rotary encoder, 1.3" SH1106 SPI OLED display, and nRF24L01+ RF transceiver.</em>
+  <em><b>Figure 1:</b> Phase 1 Top View — ESP32-S3-N16R8 module, nRF24L01+ RF transceiver, 100 µF bulk decoupling capacitor, peripheral male pin headers, and dedicated power rail male headers on a 6×9 cm perfboard.</em>
 </p>
 
 <p align="center">
   <img src="images/SIDE_VIEW_WITH_ANTENNA.png" alt="Multi-Functional Controller Profile & RF Antenna" width="700">
   <br>
-  <em><b>Figure 2:</b> Ergonomic profile — 2.4 GHz external dipole antenna connected to the nRF24L01+ transceiver, rotary dial, and dual USB-C ports.</em>
+  <em><b>Figure 2:</b> Phase 1 Side Profile — 2.4 GHz external dipole antenna mounted to the nRF24L01+ module and dual USB-C ports (Native USB-OTG & UART).</em>
 </p>
 
 <p align="center">
   <img src="images/BOTTOM_VIEW.png" alt="Multi-Functional Controller Perfboard Soldering" width="700">
   <br>
-  <em><b>Figure 3:</b> Underbody point-to-point bus routing — 6×9 cm perfboard with dedicated decoupled power rails (100 µF smoothing capacitor across nRF24L01+ VCC/GND) and direct FSPI signal lines.</em>
+  <em><b>Figure 3:</b> Phase 1 Underbody Bus Routing — Point-to-point solder bridges, common ground/power rails, and FSPI signal routing between the ESP32-S3-N16R8 and male breakout headers.</em>
 </p>
 
 ---
 
-## Key Hardware & Firmware Architecture
+## Phase 2: Console Expansion Bill of Materials (BOM)
 
-- **Microcontroller Core:** Espressif **ESP32-S3-N16R8** (16 MB Quad SPI Flash, 8 MB Octal PSRAM) running FreeRTOS.
+The project is transitioning from the bare perfboard carrier into a self-contained console transmitter. Below is the complete English technical specification for the Phase 2 hardware expansion:
-- **Collision-Free Shared FSPI (`SPI2_HOST`) Bus:**
+
-  - Shares `MOSI` (`GPIO 11`), `MISO` (`GPIO 13`), and `SCK` (`GPIO 12`) between the **1.3" SH1106 OLED** (10 MHz clock) and the **nRF24L01+ 2.4 GHz Transceiver** (1 MHz clock) via independent hardware Chip Select lines (`GPIO 10` and `GPIO 14`).
+| Category | Component (English Technical Name) | Original / Part Spec | Engineering Role in Controller |
-- **Bare-Metal 5×8 OLED Graphics Engine & Multi-Screen UI State Machine:**
+| :--- | :--- | :--- | :--- |
-  - Direct register-level driver for the 1.3" SH1106 controller (handling the 132×64 internal RAM 2-pixel column offset) with a complete 5×8 bitmap font table (`A–Z`, `0–9`, `<`, `>`, `[`, `]`, `(`, `)`, `/`, `-`, `:`, `.`).
+| **Enclosure** | **DT-100 Desktop Instrument Enclosure (Black ABS)** | `DT-100` (`190 × 137 × 59 mm`) | Main desktop/handheld transmitter chassis housing the perfboard, dual gimbals, screen, and battery pack. |
-  - **4 Interactive Screens:**
+| **Display** | **1.3" ST7789 IPS TFT Color LCD Module** | `240 × 240 px`, RGB SPI, 3.3V | High-contrast full-color IPS graphical dashboard replacing the benchtop monochrome OLED. |
-    1. `DRIVE VEHICLE`: Real-time One-Shot `ADC1` joystick acquisition (`VRx` / `VRy`) and live 2.4 GHz packet broadcasting (`rc_packet_t`).
+| **Primary Input** | **2× Dual-Axis Hall-Effect Analog Joysticks** | Contactless Magnetic 2-Axis | Drift-free 4-channel analog control (Throttle, Yaw, Pitch, Roll) routed to `ADC1`. |
-    2. `RADIO CONFIG`: Verifies physical nRF24L01+ SPI link (`SETUP_AW` register `0x03`) and tunes `RF_CH` (register `0x05`) live across channels `0–125` (`2.400–2.525 GHz`) using the rotary dial.
+| **Audio Input** | **MAX4466 Electret Microphone Amplifier Module** | Adjustable Gain, `2.4V–5.5V` | Analog voice telemetry capture and real-time audio FFT spectrum visualization on `ADC1`. |
-    3. `CALIBRATE`: Live raw `ADC1` readout (`0–4095`) with one-click neutral center-point capture.
+| **Storage** | **SPI MicroSD Card Reader Module** | Standard SPI (`MOSI/MISO/SCK/CS`) | Non-volatile storage for flight/drive telemetry logs, model profiles, and UI bitmap assets. |
-    4. `SYSTEM INFO`: Displays target silicon (`ESP32-S3`) and real-time free RTOS heap memory (`esp_get_free_heap_size()`).
+| **Power Boost** | **MT3608 2A Adjustable DC-DC Step-Up Boost Converter** | `2V–24V` Input, up to `28V` / `2A` Out | Boosts the 3.7V Li-ion battery rail to `5V` / `12V` for auxiliary peripherals and switch LED illumination. |
-- **Hardware Quadrature Rotary Decoder (`pulse_cnt`):**
+| **Master Switch** | **12–24V Illuminated Waterproof Push-Button Switch** | Latching ON-OFF, White LED Ring | Master system power / RF arming switch mounted on the DT-100 front panel. |
-  - Uses the ESP32-S3 hardware Pulse Counter peripheral on `GPIO 15` (`CLK`) and `GPIO 16` (`DT`) with a `1000 ns` hardware glitch filter and full 4× quadrature edge/level state decoding, paired with a `300 ms` debounced push-switch (`GPIO 17`).
+| **Mode Switch** | **KTS-303 Mini Toggle Switch (3-Pin SPDT)** | `ON-OFF`, Panel Mount | Physical toggle switch for flight/drive mode selection or high/low rate switching. |
-- **Wi-Fi-Safe Analog Joystick Acquisition (`ADC1`):**
+| **Aux Switch** | **180° Vertical Slide Switch** | `ON-OFF` Slide, Through-Hole | Sub-circuit power rail isolation / programming mode selector. |
-  - Routes `VRx` (`GPIO 4`, `ADC1_CH3`) and `VRy` (`GPIO 5`, `ADC1_CH4`) with `12 dB` attenuation (`0–3.3V` full-scale) on `ADC_UNIT_1` to avoid `ADC2` Wi-Fi/RF arbitration conflicts.
+| **Power Diode** | **1N5817 Schottky Barrier Diode** | `1A`, `20V`, `DO-41` THT | Low forward-voltage drop ($V_F \approx 0.45\text{V}$) power rail OR-ing and reverse-polarity protection. |
-- **Power Subsystem:**
+| **Rectifier Diode** | **1N4001 General-Purpose Silicon Diode** | `1A`, `50V`, `DO-41` THT | Reverse-current blocking and inductive flyback protection across switched loads. |
-  - Dual parallel 18650 Li-ion cells delivering **4800 mAh** combined capacity.
+| **Switching BJT** | **2N2222 NPN Bipolar Junction Transistor** | `40V`, `600mA–800mA`, `TO-92` | Low-side transistor switch allowing 3.3V ESP32-S3 GPIOs to drive the 12V switch LED ring (via MT3608) or buzzers. |
-  - 100 µF low-ESR electrolytic bulk decoupling capacitor suppressing nRF24L01+ TX current spikes.
 
 ---
 
-## GPIO Pinout & Peripheral Mapping (ESP32-S3 Hardware Specification)
+## Verified Pin Mapping (Phase 1 Firmware & Bench Harness)
 
-The physical controller uses a shared high-speed **SPI2_HOST** (FSPI) bus for both the 1.3" SH1106 OLED and the nRF24L01+ RF transceiver, alongside dedicated `ADC1` channels and hardware pulse-counter inputs:
+The master firmware (`firmware/main/mmcontroller.c`) configures a collision-free shared **SPI2_HOST** (FSPI) bus, `ADC1` analog inputs, and the hardware `pulse_cnt` quadrature decoder:
 
 | Peripheral / Signal | GPIO | Hardware Interface | Description |
 | :--- | :---: | :--- | :--- |
-| **SPI Bus: MOSI** | `GPIO 11` | SPI Master Output (`SPI2_HOST`) | Shared data line for nRF24L01+ and OLED (`SDA` / `D1`) |
+| **SPI Bus: MOSI** | `GPIO 11` | SPI Master Output (`SPI2_HOST`) | Shared data line for nRF24L01+, Display (`SDA`), and MicroSD |
-| **SPI Bus: MISO** | `GPIO 13` | SPI Master Input (`SPI2_HOST`) | Data line from nRF24L01+ radio module |
+| **SPI Bus: MISO** | `GPIO 13` | SPI Master Input (`SPI2_HOST`) | Shared data input line from nRF24L01+ and MicroSD |
-| **SPI Bus: SCK (Clock)** | `GPIO 12` | SPI Master Clock (`SPI2_HOST`) | Shared clock line for nRF24L01+ and OLED (`CLK` / `D0`) |
+| **SPI Bus: SCK (Clock)** | `GPIO 12` | SPI Master Clock (`SPI2_HOST`) | Shared clock line for nRF24L01+, Display (`CLK`), and MicroSD |
 | **nRF24L01+ Chip Select (CS)** | `GPIO 14` | SPI Device Select | Dedicated radio bus enable |
 | **nRF24L01+ Chip Enable (CE)** | `GPIO 21` | Digital Output | Radio TX/RX power state activation line |
-| **OLED Chip Select (CS)** | `GPIO 10` | SPI Device Select | Display SPI bus enable |
+| **Display Chip Select (CS)** | `GPIO 10` | SPI Device Select | Display SPI bus enable |
-| **OLED Data/Command (DC)** | `GPIO 9` | Digital Output | 1.3" OLED command vs. data selection |
+| **Display Data/Command (DC)** | `GPIO 9` | Digital Output | Display command vs. frame data selection |
-| **OLED Reset (RES)** | `GPIO 8` | Digital Output | Hardware display reset line |
+| **Display Reset (RES)** | `GPIO 8` | Digital Output | Hardware display reset line |
-| **Joystick VRx (X-Axis)** | `GPIO 4` | `ADC1` Channel 3 (`12 dB` Atten) | Analog X-axis potentiometer input (`0–3.3V` safe) |
+| **Joystick 1 VRx (X-Axis)** | `GPIO 4` | `ADC1` Channel 3 (`12 dB` Atten) | Analog X-axis input (`0–3.3V` safe) |
-| **Joystick VRy (Y-Axis)** | `GPIO 5` | `ADC1` Channel 4 (`12 dB` Atten) | Analog Y-axis potentiometer input (`0–3.3V` safe) |
+| **Joystick 1 VRy (Y-Axis)** | `GPIO 5` | `ADC1` Channel 4 (`12 dB` Atten) | Analog Y-axis input (`0–3.3V` safe) |
 | **Rotary Encoder CLK** | `GPIO 15` | ESP-IDF `pulse_cnt` Unit | Quadrature channel A (hardware edge counter) |
 | **Rotary Encoder DT** | `GPIO 16` | ESP-IDF `pulse_cnt` Unit | Quadrature channel B (direction sensing) |
 | **Rotary Encoder Switch (SW)**| `GPIO 17` | Digital Input (`PULLUP`) | Push-button (menu enter/select mode) |
@@ -80,7 +85,7 @@ The physical controller uses a shared high-speed **SPI2_HOST** (FSPI) bus for bo
 ### Silicon Multiplexing Notes (ESP32-S3-N16R8 vs. Classic ESP32)
 1. **Octal PSRAM & Flash Reservation (`GPIO 26 – GPIO 37`):** On the **ESP32-S3-N16R8** (8 MB Octal PSRAM), `GPIO 26` through `GPIO 37` are wired internally to the Octal SPI Flash/PSRAM bus. Accessing `GPIO 26, 27, 32, 33` triggers an immediate *Guru Meditation Error / Cache Disabled Panic* on boot.
 2. **Unbonded Silicon Pins (`GPIO 22 – GPIO 25`):** `GPIO 22, 23, 24, 25` do not exist on the ESP32-S3 pin multiplexing matrix.
-3. **FSPI (`SPI2_HOST`) Default Matrix:** Uses native ESP32-S3 FSPI pins (`GPIO 10, 11, 12, 13`) for zero-penalty IOMUX/GPIO matrix routing rather than legacy 2016 ESP32 VSPI defaults (`GPIO 5, 18, 23`).
+3. **FSPI (`SPI2_HOST`) Default Matrix:** Uses native ESP32-S3 FSPI pins (`GPIO 10, 11, 12, 13`) rather than legacy 2016 ESP32 VSPI defaults (`GPIO 5, 18, 23`).
 
 ---
 
@@ -90,18 +95,18 @@ The physical controller uses a shared high-speed **SPI2_HOST** (FSPI) bus for bo
 multi-functional-controller/
 ├── firmware/                        # ESP-IDF C99 Firmware Project (ESP32-S3)
 │   ├── CMakeLists.txt               # Top-level CMake project configuration
-│   ├── sdkconfig                    # ESP32-S3 target configuration
+│   ├── sdkconfig                    # Verified ESP32-S3 target configuration
 │   └── main/
 │       ├── CMakeLists.txt           # Component registration
-│       └── mmcontroller.c           # Master firmware: Shared SPI2, SH1106 5x8 UI, nRF24L01+, PCNT, ADC1
+│       └── mmcontroller.c           # Master firmware: Shared SPI2, Display UI, nRF24L01+, PCNT, ADC1
 ├── hardware/                        # KiCad 10 Electronic Design Automation (EDA)
 │   ├── mfc-1.kicad_pro              # KiCad project file
-│   ├── mfc-1.kicad_sch              # Complete schematic design & component symbols
+│   ├── mfc-1.kicad_sch              # Phase 1 schematic design (ESP32-S3, nRF24L01+, 100uF cap)
 │   └── mfc-1.kicad_pcb              # Board layout & routing rules
-├── images/                          # High-resolution prototype photography
+├── images/                          # High-resolution Phase 1 prototype photography
-│   ├── TOP_VIEW.png                 # Front control surface overview
+│   ├── TOP_VIEW.png                 # Perfboard top view (MCU, RF, 100uF cap, male pin headers)
 │   ├── SIDE_VIEW_WITH_ANTENNA.png   # RF antenna and profile perspective
-│   └── BOTTOM_VIEW.png              # Perfboard underside bus wiring
+│   └── BOTTOM_VIEW.png              # Perfboard underside solder bus & power rail wiring
 ├── .gitignore                       # Clean repository filter (builds, caches, local configs)
 ├── LICENSE                          # MIT License
 └── README.md                        # Master engineering documentation
@@ -111,61 +116,27 @@ multi-functional-controller/
 
 ## Getting Started: Building the Firmware
 
-### Prerequisites
+```bash
-- [ESP-IDF v5.1+](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/get-started/) installed and exported into your environment:
+. $HOME/esp/esp-idf/export.sh
-  ```bash
+cd firmware
-  . $HOME/esp/esp-idf/export.sh
+idf.py set-target esp32s3
-  ```
+idf.py build
-
+idf.py -p /dev/ttyACM0 flash monitor
-### Build & Flash
+```
-
-1. Navigate to the firmware directory:
-   ```bash
-   cd firmware
-   ```
-
-2. Set target to ESP32-S3:
-   ```bash
-   idf.py set-target esp32s3
-   ```
-
-3. Compile the firmware:
-   ```bash
-   idf.py build
-   ```
-
-4. Flash to the controller and open serial monitoring:
-   ```bash
-   idf.py -p /dev/ttyACM0 flash monitor
-   ```
 
 ---
 
-## Hardware CAD & Schematic Editing
+## Project Status & Roadmap
 
-The electronic schematic is developed in **KiCad 10**:
+- [x] **Phase 1 Hardware (Complete):** 6×9 cm perfboard carrier assembly with ESP32-S3-N16R8, nRF24L01+ RF module, 100 µF decoupling capacitor, signal male headers, and power rail male headers.
-
+- [x] **Phase 1 Firmware (Complete):** Shared `SPI2_HOST` bus, 5×8 UI state machine (`DRIVE VEHICLE`, `RADIO CONFIG`, `CALIBRATE`, `SYSTEM INFO`), hardware `pulse_cnt` rotary decoding, and live nRF24 channel tuning (`0–125`).
-1. Open the project:
+- [ ] **Phase 2 Hardware Integration (In Progress):**
-   ```bash
+  - [ ] Mount system into **DT-100 (`190 × 137 × 59 mm`)** black desktop enclosure.
-   kicad hardware/mfc-1.kicad_pro
+  - [ ] Integrate **2× Dual-Axis Hall-Effect Joysticks** (`ADC1` channels `GPIO 4, 5, 6, 7`).
-   ```
+  - [ ] Upgrade display to **1.3" ST7789 240×240 IPS TFT LCD**.
-2. Inspect or modify the schematic in `eeschema` (`hardware/mfc-1.kicad_sch`).
+  - [ ] Wire **MT3608 DC-DC Boost Converter**, **1N5817 / 1N4001 Diodes**, and **2N2222 NPN BJT** to drive the **12–24V Illuminated Push-Button Switch**, **KTS-303 Toggle Switch**, and **180° Slide Switch**.
-3. To generate vector schematics for documentation or web publication:
+  - [ ] Integrate **MAX4466 Microphone Amplifier** and **SPI MicroSD Card Module**.
-   - Select **File $\rightarrow$ Plot $\rightarrow$ SVG** or **PDF**.
+- [ ] **Phase 3 Custom PCB:** Full multi-layer PCB fabrication in KiCad 10.
-
----
-
-## Roadmap & Milestones
-
-- [x] Initial hardware breadboard and perfboard prototype (6×9 cm assembly).
-- [x] Shared `SPI2_HOST` bus driving both 1.3" SH1106 OLED and nRF24L01+ without bus collisions.
-- [x] Full 5×8 bare-metal font renderer (`A–Z`, `0–9`, and UI punctuation/symbols).
-- [x] Hardware pulse-counter (`pulse_cnt`) quadrature decoder with 1000 ns glitch filter & 300 ms debounced state machine.
-- [x] Live nRF24L01+ SPI register verification (`0x03`) and channel tuning (`0–125`) with `ADC1` joystick packet transmission.
-- [ ] Custom multi-layer printed circuit board (PCB) design in KiCad.
-- [ ] 3D-printable ergonomic handheld enclosure (PETG / Resin).
-- [ ] Bidirectional ACK-payload telemetry from target RC vehicle.
-- [ ] Native USB Gamepad HID descriptor integration on ESP32-S3 USB-OTG port.
 
 ---