diff --git a/README.md b/README.md
index 87dc847..26abcb4 100644
--- a/README.md
+++ b/README.md
@@ -15,48 +15,85 @@
---
-## 2. Current Situation & Hardware Prototype
+## 2. Current Situation & Early Prototype Showcase (Rev 0.1)
-- **Controller Prototype:** Currently prototyped on a **6×9 cm perfboard**. The `ESP32-S3-N16R8` communicates over a shared `SPI2_HOST` bus with a Nordic `nRF24L01+` 2.4 GHz transceiver and a temporary 1.3" SH1106 OLED display, decoupled by a `100 µF` electrolytic capacitor across the radio rails.
-- **Firmware:** A deterministic FreeRTOS state machine (`firmware/main/mmcontroller.c`) handles hardware quadrature decoding (`PCNT`) for a `KY-040` rotary encoder menu UI, `300 ms` software button debouncing, `ADC1` joystick polling, and live 2.4 GHz RF channel configuration (`0–125`).
-- **Display Hardware Pivot (`1.3" OLED` $\rightarrow$ `1.8" ST7789 TFT`):** Bench testing revealed that the 7-pin 1.3" OLED module lacks a physical Chip Select (`CS`) pin, causing SPI bus collisions when sharing the bus. We are upgrading to a **1.8" ST7789 Color TFT LCD** (which exposes a dedicated hardware `CS` pin on `GPIO 10`) to share the SPI bus safely without bus contention.
+> [!NOTE]
+> **Early Prototype Notice (Rev 0.1 Carrier Build):**
+> The photographs and schematic below represent the **very early initial stage** of the physical hardware build. At this stage, only the core carrier foundation is soldered onto the 6×9 cm perfboard: the **ESP32-S3-N16R8 microcontroller**, **nRF24L01+ 2.4 GHz radio module**, **100 µF electrolytic burst-smoothing capacitor**, **signal male pin headers**, and **power rail male headers**.
+> The repository's firmware (`firmware/main/mmcontroller.c`) and schematic (`hardware/mfc-1.kicad_sch`) are intentionally kept matched to this verified **Rev 0.1 hardware baseline**. As the new modules (`1.8" ST7789 TFT`, `K-Silver PS5 Hall-Effect Joysticks`, `MicroSD`, `MAX4466`, `2N2222` buzzer stage, and enclosure) are physically integrated, both the hardware photos and firmware will be updated step-by-step.
+
+- **Controller Prototype (Rev 0.1):** Prototyped on a **6×9 cm perfboard**. The `ESP32-S3-N16R8` communicates over a shared `SPI2_HOST` bus with a Nordic `nRF24L01+` 2.4 GHz transceiver and a temporary benchtop 1.3" SH1106 OLED display connected via the male breakout headers.
+- **Current Baseline Firmware:** A deterministic FreeRTOS state machine (`firmware/main/mmcontroller.c`) handles hardware quadrature decoding (`PCNT`) for a `KY-040` rotary encoder menu UI, `300 ms` software button debouncing, and live 2.4 GHz RF channel configuration (`0–125`).
+- **Display Hardware Pivot (`1.3" OLED` $\rightarrow$ `1.8" ST7789 TFT`):** Bench testing revealed that the 7-pin 1.3" OLED module lacks a physical Chip Select (`CS`) pin (hard-tied to GND internally), causing SPI bus collisions when sharing the bus. We are upgrading to a **1.8" ST7789 Color TFT LCD** (which exposes a dedicated hardware `CS` pin on `GPIO 10`) to share the SPI bus safely without bus contention.
- **Manufacturing & Enclosure Status:** Paused cutting the rigid ABS plastic project box (`DT-100`, `190 × 137 × 59 mm`) until next month when a variable 3-speed rotary tool (`Dremel/E108`) and `2.35 mm` diamond cutting wheels arrive to ensure clean, professional cutouts without melting the ABS plastic.
- Figure 1: 6×9 cm Perfboard Controller Prototype (Top View) — ESP32-S3-N16R8 module, nRF24L01+ 2.4 GHz transceiver, 100 µF burst-smoothing capacitor, peripheral male header bus, and power rail headers.Figure 1 (Early Build — Rev 0.1): Initial 6×9 cm perfboard carrier top view — ESP32-S3-N16R8 module, nRF24L01+ 2.4 GHz transceiver, 100 µF decoupling capacitor, peripheral male pin headers, and power rail male headers. (Will be updated as Phase 2 modules are installed).
- Figure 2: Side Profile — External 2.4 GHz SMA dipole antenna connected to the nRF24L01+ transceiver and dual USB-C ports (Native USB-OTG & UART).Figure 2 (Early Build — Rev 0.1): Side profile showing the external 2.4 GHz SMA dipole antenna connected to the nRF24L01+ transceiver and dual USB-C ports (Native USB-OTG & UART).
- Figure 3: Underbody Bus Routing — Point-to-point solder bridges, common ground/power rails, and shared SPI2 signal routing on the 6×9 cm perfboard.Figure 3 (Early Build — Rev 0.1): Underbody point-to-point solder bridges, common ground/power rails, and shared SPI2 signal routing on the 6×9 cm perfboard.
+
+### Rev 0.1 Core Carrier Schematic (`hardware/mfc-1.kicad_sch`)
+
+
+ Figure 4: KiCad 10 schematic of the Rev 0.1 Core Carrier (`U1: ESP32-S3`, `U2: nRF24L01+`, `C1: 100 µF` decoupling capacitor).
---
-## 3. Hardware Architecture & Bill of Materials (BOM)
+## 3. Dual-Node System Architecture & Bill of Materials (BOM)
+
+```mermaid
+flowchart LR
+ subgraph TX["Node 1: Handheld Controller (ESP32-S3-N16R8)"]
+ MCU["ESP32-S3-N16R8
+SVG Image created as mfc-1.svg date 2026-10-18T01:21:08
+ Image generated by Eeschema-SVG
+
+
+
+
+
+1
+1
+2
+2
+3
+3
+4
+4
+5
+5
+6
+6
+1
+1
+2
+2
+3
+3
+4
+4
+5
+5
+6
+6
+A
+A
+B
+B
+C
+C
+D
+D
+A
+A
+B
+B
+C
+C
+D
+D
+Date:
+Date:
+KiCad E.D.A. 10.0.7
+KiCad E.D.A. 10.0.7
+
+
+Rev:
+Rev:
+
+
+Size: A4
+Size: A4
+Id: 1/1
+Id: 1/1
+
+
+Title:
+Title:
+
+
+File: mfc-1.kicad_sch
+File: mfc-1.kicad_sch
+Sheet: /
+Sheet: /
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+GND
+GND
+
+
+1
+1
+
+
+
+
+VCC
+VCC
+
+
+2
+2
+
+
+
+
+
+CE
+
+CE
+
+
+
+3
+
+3
+
+
+
+
+
+~{CSN}
+
+~{CSN}
+
+
+
+4
+
+4
+
+
+
+
+
+SCK
+
+SCK
+
+
+
+5
+
+5
+
+
+
+
+
+MOSI
+
+MOSI
+
+
+
+6
+
+6
+
+
+
+
+
+MISO
+
+MISO
+
+
+
+7
+
+7
+
+
+
+
+
+IRQ
+
+IRQ
+
+
+
+8
+
+8
+
+
+U2
+U2
+NRF24L01_Breakout
+NRF24L01_Breakout
+
+
+
+
+
+
+
+
+C1
+C1
+100 microfarad
+100 microfarad
+
+
+
+
+
+
+
+
+
+SPICLK_N
+
+SPICLK_N
+
+
+
+36
+
+36
+
+
+
+
+
+MTDO
+
+MTDO
+
+
+
+45
+
+45
+
+
+
+
+
+GPIO45
+
+GPIO45
+
+
+
+51
+
+51
+
+
+
+
+
+LNA_IN
+
+LNA_IN
+
+
+
+1
+
+1
+
+
+
+
+VDD3P3
+VDD3P3
+
+
+2
+2
+
+
+
+
+
+CHIP_PU
+
+CHIP_PU
+
+
+
+4
+
+4
+
+
+
+
+
+GPIO0
+
+GPIO0
+
+
+
+5
+
+5
+
+
+
+
+
+GPIO1
+
+GPIO1
+
+
+
+6
+
+6
+
+
+
+
+
+GPIO2
+
+GPIO2
+
+
+
+7
+
+7
+
+
+
+
+
+GPIO3
+
+GPIO3
+
+
+
+8
+
+8
+
+
+
+
+
+GPIO4
+
+GPIO4
+
+
+
+9
+
+9
+
+
+
+
+
+GPIO5
+
+GPIO5
+
+
+
+10
+
+10
+
+
+
+
+
+GPIO6
+
+GPIO6
+
+
+
+11
+
+11
+
+
+
+
+
+GPIO7
+
+GPIO7
+
+
+
+12
+
+12
+
+
+
+
+
+GPIO8
+
+GPIO8
+
+
+
+13
+
+13
+
+
+
+
+
+GPIO9
+
+GPIO9
+
+
+
+14
+
+14
+
+
+
+
+
+GPIO10
+
+GPIO10
+
+
+
+15
+
+15
+
+
+
+
+
+GPIO11
+
+GPIO11
+
+
+
+16
+
+16
+
+
+
+
+
+GPIO12
+
+GPIO12
+
+
+
+17
+
+17
+
+
+
+
+
+GPIO13
+
+GPIO13
+
+
+
+18
+
+18
+
+
+
+
+
+GPIO14
+
+GPIO14
+
+
+
+19
+
+19
+
+
+
+
+VDD3P3_RTC
+VDD3P3_RTC
+
+
+20
+20
+
+
+
+
+
+XTAL_32K_P
+
+XTAL_32K_P
+
+
+
+21
+
+21
+
+
+
+
+
+XTAL_32K_N
+
+XTAL_32K_N
+
+
+
+22
+
+22
+
+
+
+
+
+GPIO17
+
+GPIO17
+
+
+
+23
+
+23
+
+
+
+
+
+GPIO18
+
+GPIO18
+
+
+
+24
+
+24
+
+
+
+
+
+GPIO19/USB_D-
+
+GPIO19/USB_D-
+
+
+
+25
+
+25
+
+
+
+
+
+GPIO20/USB_D+
+
+GPIO20/USB_D+
+
+
+
+26
+
+26
+
+
+
+
+
+GPIO21
+
+GPIO21
+
+
+
+27
+
+27
+
+
+
+
+
+SPICS1
+
+SPICS1
+
+
+
+28
+
+28
+
+
+
+
+VDD_SPI
+VDD_SPI
+
+
+29
+29
+
+
+
+
+
+SPIHD
+
+SPIHD
+
+
+
+30
+
+30
+
+
+
+
+
+SPIWP
+
+SPIWP
+
+
+
+31
+
+31
+
+
+
+
+
+SPICS0
+
+SPICS0
+
+
+
+32
+
+32
+
+
+
+
+
+SPICLK
+
+SPICLK
+
+
+
+33
+
+33
+
+
+
+
+
+SPIQ
+
+SPIQ
+
+
+
+34
+
+34
+
+
+
+
+
+SPID
+
+SPID
+
+
+
+35
+
+35
+
+
+
+
+
+SPICLK_P
+
+SPICLK_P
+
+
+
+37
+
+37
+
+
+
+
+
+GPIO33
+
+GPIO33
+
+
+
+38
+
+38
+
+
+
+
+
+GPIO34
+
+GPIO34
+
+
+
+39
+
+39
+
+
+
+
+
+GPIO35
+
+GPIO35
+
+
+
+40
+
+40
+
+
+
+
+
+GPIO36
+
+GPIO36
+
+
+
+41
+
+41
+
+
+
+
+
+GPIO37
+
+GPIO37
+
+
+
+42
+
+42
+
+
+
+
+
+GPIO38
+
+GPIO38
+
+
+
+43
+
+43
+
+
+
+
+
+MTCK
+
+MTCK
+
+
+
+44
+
+44
+
+
+
+
+VDD3P3_CPU
+VDD3P3_CPU
+
+
+46
+46
+
+
+
+
+
+MTDI
+
+MTDI
+
+
+
+47
+
+47
+
+
+
+
+
+MTMS
+
+MTMS
+
+
+
+48
+
+48
+
+
+
+
+
+U0TXD
+
+U0TXD
+
+
+
+49
+
+49
+
+
+
+
+
+U0RXD
+
+U0RXD
+
+
+
+50
+
+50
+
+
+
+
+
+GPIO46
+
+GPIO46
+
+
+
+52
+
+52
+
+
+
+
+
+XTAL_N
+
+XTAL_N
+
+
+
+53
+
+53
+
+
+
+
+
+XTAL_P
+
+XTAL_P
+
+
+
+54
+
+54
+
+
+
+
+VDDA
+VDDA
+
+
+55
+55
+
+
+
+
+GND
+GND
+
+
+57
+57
+
+
+U1
+U1
+ESP32-S3
+ESP32-S3
+
+
+
+
+
+
+
+
+
+
+ 
+ 
+ 
+